As shown in FIG. 1, a typical computer system 10 has, among other components, a microprocessor 12, one or more forms of memory 14, integrated circuits 16 having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths 19, e.g., wires, buses, etc., to accomplish the various tasks of the computer system 10.
In order to properly accomplish such tasks, the computer system 10 relies on the basis of time to coordinate its various operations. To that end, a crystal oscillator 18 generates a system clock signal (referred to and known in the art as xe2x80x9creference clockxe2x80x9d and shown in FIG. 1 as SYS_CLK) to various parts of the computer system 10. Modern microprocessors and other integrated circuits, however, are typically capable of operating at frequencies significantly higher than the system clock, and thus, it becomes important to ensure that operations involving the microprocessor 12 and the other components of the computer system 10 use a proper and accurate reference of time.
One component used within the computer system 10 to ensure a proper reference of time among a system clock and a microprocessor clock, i.e., xe2x80x9cchip clock,xe2x80x9d is a type of clock generator known as a phase locked loop, or xe2x80x9cPLLxe2x80x9d 20. The PLL 20 is an electronic circuit that controls an oscillator such that the oscillator maintains a constant phase relative to a reference signal. Referring to FIG. 1, the PLL 20 has as its input the system clock, which is its reference signal, and outputs a chip clock signal (shown in FIG. 1 as CHIP_CLK) to the microprocessor 12. The system clock and chip clock have a specific phase and frequency relationship controlled by the PLL 20. This relationship between the phases and frequencies of the system clock and chip clock ensures that the various components within the microprocessor 12 use a controlled and accounted for reference of time. When this relationship is not maintained by the PLL 20, however, the operations within the computer system 10 become non-deterministic.
FIG. 2 shows a PLL 20. The PLL 20 comprises a feedback loop that aligns the transition edge and frequency of the system clock 41 and a feedback loop signal 40. The PLL 20 adjusts the output frequency in order to zero any phase and frequency difference between the system clock 41 and the feedback loop signal 40. The addition of a divide-by-N circuit 39 in the feedback loop enables the PLL 20 to generate an output that has a frequency of N times the system clock 41 frequency. Multiplying the system clock is useful when the chip clock 42 must have a higher frequency than the system clock 41. The PLL core 36 adjusts the output frequency in order to zero any phase and frequency difference between the system clock 41 and the feedback loop signal 40. By adding the divide by N block 39, the chip clock 42 must be N times faster to allow the phase and frequency difference between the system clock 41 and the feedback loop signal 40 to zero. The PLL 20 may also have buffers 37 and 38 to drive a larger resistive and/or capacitive load. The buffers 37 and 38 are in the feedback loop so that any phase shift created by the buffers 37 and 38 is zeroed by the PLL core 36.
One common performance measure for a PLL is jitter. Jitter is the time domain error from poor spectral purity of an output. In other words, in a repeated output pattern, such as a clock signal, a transition that occurs from one state to another does not happen at the same time relative to other transitions. Jitter represents the perturbations that result in the intermittent shortening or lengthening of signal elements of an output. The system clock may have jitter that may need to be filtered by the PLL. The PLL may need to follow and compensate for jitter at the PLL output.
Phase locked loops are basically second order feedback control systems. As such, the phase locked loop can be described in the frequency domain as having a damping factor and natural frequency. The damping factor and natural frequency are fixed by the selection of the PLL circuit parameters. The loop bandwidth is defined as the PLL input frequency at which the PLL output magnitude is 3 dB lower than the PLL output magnitude when the PLL input frequency is zero (DC). The loop bandwidth determines to a large degree the speed at which the phase locked loop can react to a disturbance. The PLL should have a low loop bandwidth so that input clock jitter is filtered. Power supply noise will, however, have a certain noise-versus-frequency characteristic. The PLL loop bandwidth may need to be increased to recover from the generation of output jitter caused by power supply noise.
According to one aspect of the present invention, a phase locked loop comprises: a voltage controlled oscillator that generates an output clock signal dependent on an input thereto; an input receiver comprising an input clock path and a feedback clock path, where the input receiver is configured to substantially match a delay of an input clock signal through the input clock path and a delay of a feedback clock signal through the feedback clock path, and where the feedback clock signal is dependent on the output clock signal; a phase frequency detector that detects a phase difference between the substantially delay matched input and feedback clock signals; and a bias generator, responsive to the phase frequency detector, arranged to provide a voltage to the input of the voltage controlled oscillator.
According to another aspect, an integrated circuit comprises a clock path used for propagating a system clock, a clock distribution network used for propagating a chip clock, and a phase locked loop that generates the chip clock based on the system clock, where the phase locked loop comprises: a voltage controlled oscillator that generates an output clock signal dependent on an input thereto; an input receiver configured to substantially match delays through the input receiver of the system clock and a feedback clock; a phase frequency detector that detects a phase difference between the substantially delay matched system and chip clocks; and a bias generator, responsive to the phase frequency detector, arranged to provide a voltage to the input of the voltage controlled oscillator.
According to another aspect, an integrated circuit that has a phase locked loop that inputs an input clock signal comprises: oscillator means for generating an output clock signal; delay matching means for substantially matching delays through the delay matching means of the input clock signal and a feedback clock signal, where the feedback clock signal is dependent on the output clock signal; comparing means for comparing the substantially delay matched input clock and feedback clock signals; and means for generating a voltage to the oscillator means based on the comparing means.
According to another aspect, a method for performing phase locked loop operations comprises: inputting an input clock signal and a feedback clock signal; buffering the input clock signal and the feedback clock signal, where the buffering comprises substantially matching delays of the input clock signal and the feedback clock signal; comparing the substantially delay matched input and feedback clock signals; and generating an output clock signal based on the comparison.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.